This invention relates to the field of power supplies for integrated circuits, and in particular to power-on management for on-chip voltage down-converters.
On-chip voltage down-converters are widely used in integrated circuits, such as memory devices.
FIG. 1 shows a prior art voltage down-converter in which a differential amplifier 14 drives the gate 15 of a p-channel MOS transistor 16 with its source 17 connected to the external power supply 11, Vcc_EXT, and its drain 18 connected to the internal power supply, Vcc_INT, node 9. The first amplifier input 13 is at internal reference voltage, Vref, by connection to reference generator circuit 12; the control loop is closed by connecting the second amplifier input 8 to the Vcc_INT node 9. As the current consumption of the load circuit 19 increases, Vcc_INT will decrease; eventually Vcc_INT falls below Vref and the amplifier responds by lowering P_GATE, which increases the conductivity of the p-channel of transistor 16, resulting in an increased current flow to the Vcc_INT node 9. For applications such as flash memory, in which the current consumption has fast transients and high peak currents, the circuit of FIG. 1 has an inadequate high frequency response, to the extent that large drops in Vcc_INT occur at the onset of a fast current transient; the inadequate high frequency response is to a large extent due to the RC constant of the Vcc_INT node 9. An improved circuit, to overcome this deficiency, is shown in FIG. 2.
The prior art voltage down-converter in FIG. 2 is basically comprised of: a power device, transistor 31, providing current at the Vcc_INT node 32; a replica device with scaled W/L, transistor. 26; and a differential amplifier 23 with a feedback loop closed on the replica device, for regulating G_REF so as to keep Vcc_REF within a desired voltage range. The power device of the circuit is a source follower n-channel MOS transistor 31 with a very low threshold voltage. This transistor 31 has a very large W/L, ensuring its operation in the weak inversion region; this allows a small Vgs variation, even with the wide range of current required by the load circuit (a few xcexcA to hundreds of mA). Coupled to the power device is a replica transistor 26 with a smaller W/L. The transistor gates are driven by G_REF, by connection to the amplifier output 24. The first amplifier input 22 is at Vref. The control loop is closed on the replica device by connection of the second amplifier input 25 to the voltage divider 28. Thus, the amplifier 23 with its feedback loop operates to keep the Vcc_REF node 27 within an allowed voltage range. Leaving the power device 31 and Vcc_INT node 32 out of the feedback loop improves the stability, bandwidth and gain control of the amplifier 23, particularly considering that the RC constant of the Vcc_INT node 32 is not well controlled. Sufficient bias currents must flow in the reference circuit, Ibias_ref 29, and regulated power circuit, Ibias_reg 35, in order to keep Vcc_REF and Vcc_INT within their allowed operating ranges; transistor 33, controlled by Vbias at its gate 34 can be used to increase Ibias_reg 35, when required. Satisfactory matching of the power device and the replica device is an issue for this circuit design. An improved circuit, to overcome this deficiency, is shown in FIG. 3.
The voltage down-converter has two modes of operation for memory devices: a stand-by mode in which the power consumption from the external supply must be very low, while providing Vcc_INT with current consumption from the device of up to 10 xcexcA; and an active mode in which the voltage down-converter must provide Vcc_INT with current consumption from the device of up to 200 mA, while keeping Vcc_INT within an allowed voltage range of 1.6V to 2V.
The prior art voltage down-converter in FIG. 3 is comprised of three sections: the replica circuit 41 that is always on and generates the control signal OUT_AMP; the stand-by section 42; and the active section 43. Each section has two n-channel transistors (47 and 48, 58 and 59, and 61 and 62) compared with the single transistor of the design shown in FIG. 2. This configuration has the following advantages: reduced total output capacitance of the op-amp 44; better control of the transition from stand-by mode to active mode; and good de-coupling between the Vcc_INT nodes 36, 38 and the control loop. The reference current Ibias_ref 29 must be very low to minimize current consumption during the stand-by mode. When the active mode is entered the reference current branch is doubled (as shown for Ibias_ref 29), thus allowing the voltage down-converter to be biased quickly; this is achieved by controlling transistor 53 with signal Vbias. Vbias is also used to control the current in transistors 55 and 57, allowing faster biasing of the active and standby sections (bias currents: Ibias_act 66 and Ibias_sby 65). Since the voltage drop at the internal supply nodes 36 and 38 for a given device load current, Iload, depends on log(Iload/Ibias), a minimum Ibias must be ensured for Vcc_INT to remain within an acceptable range.
Consideration is now given specifically to the power-on phase for the voltage down-converter. It is desired to monitor both external and internal supplies, to be able to ensure that an internal power-on starts only when an external power-on occurs. It is also desired to force the active mode of the voltage down-converter at power-on. Further, it is desired to discharge the internal supply nodes of the voltage down-converter at the start of power-on, so as to ensure that the power-on always starts from the same initial condition. Furthermore, it is desired to provide a reference voltage for operation of the voltage down-converter, at the earliest opportunity during power-on.
It is an object of the present invention to provide an on-chip power-on management system to control these various power-on functions of a voltage down-converter.
The above object has been achieved by a power-on management system for an on-chip voltage down-converter, monitoring both external and internal voltage supplies to independently determine when both supplies have reached minimum levels for proper operation of on-chip circuitry. The power-on management system supplies output signals that: control the discharge of the internal supply nodes at the initiation of power-on; force the active mode of the voltage down-converter; and deactivate a fast local voltage reference on completion of power-on. The system comprises signal level detectors and devices for delaying the falling edge of input signals.